1. Field of the Invention
The present invention relates to an apparatus, a method and a program for verifying an asynchronous circuit. More particularly, the present invention relates to an apparatus, a method and a program for verifying an asynchronous circuit, which execute function simulations at a language level for verifying the asynchronous circuit.
2. Description of the Related Art
The recent advancement of a semiconductor technology has been outstanding. For example, with an advancement of ultra-fine structure, a size of a circuit installed in a semiconductor chip has been increasing. This size increasing leads to increase processing time for a function simulation, when a computer executes a circuit design. In the function simulation, when an asynchronous circuit is included in a simulation target, an asynchronous input signal, whose cycle should be variable, is supplied to a function simulator. That results in further increase of the processing time.
As a solution to this problem, a conventional technique of Japanese Laid Open Patent Application (JP-P 2003-233638A) discloses a method for verifying an asynchronous circuit and its program. This method of verifying the asynchronous circuit verifies the asynchronous circuit constituted by sequential circuits which are verification targets by using a function simulation apparatus of a language level. This is characterized in that: transiently storing an input data for each event occurring time in one clock cycle for inner array elements preliminarily provided in the sequential circuits to hold values of the input data correspondingly to a plurality of times; when an active edge of a clock signal is detected, if the input data is changed from a value in a time previous of the active edge detection, defining this state as a metastable state; generating and outputting a value of the metastable state, and outputting the input data of any one time among the input data transiently stored for each event generation time, after a next one time.
Japanese Laid Open Patent Application (JP-P 2003-233638A) will be described in detail below. FIG. 1 is a flowchart showing the method for verifying the asynchronous circuit in the conventional technique. FIG. 1 shows an operation flow of a function simulation for sequential circuits, operated in a computer.
At first, at S111, the sequential circuit holds a value Din of an input data at a current time in an inner array element D[0]. Here, the inner array element is the array element possessed by each of flip-flop (hereinafter referred to as FF) 1, FF2 and FF3 of the sequential circuits. The inner array element holds the value of the input data Din in each FF, correspondingly to n number of times. The inner array element D has n number of array elements. The symbol n is assumed to be a value smaller than the number of events in one clock cycle used in the function simulation. The inner array element holds the input data value as follows. That is, in the inner array element, as time advances, the value is sequentially shifted such that the value of D[0] is shifted to D[1] and the value of D[n−1] is shifted to D[n]. Thus, the inner array element holds the values D[0] to D[n] corresponding to the n number of times.
Next, in a clock signal active edge detecting process at S112, an edge detection of the clock signal supplied to the sequential circuit is carried out. If an edge is detected (S112: Yes), an input data change detecting process at S113 is carried out. If the edge is not detected (S112: No), the processes of S123 and S122 are carried out.
In the input data change detecting process at S113, the change detection in the input data supplied to the sequential circuit is carried out. If the change is detected (S113: Yes), a metastable state detecting process at S114 is carried out. If the change is not detected (S113: No), the processes at S120, S121 and S122 are carried out.
In the metastable state detecting process at S114, a value of a metastable state flag is checked. If the value of the metastable state flag is “true”=it is in the metastable state (S114: Yes), the metastable state flag is set to “false” at S115. After that, at S116, as the input data to the sequential circuit, the value of any element m of the inner array element D[m] (0≦m≦n) held at the foregoing S111 is held in a storage variable d. In succession, at S117, the value in the metastable state is generated by using a random number, and the generated value is held as a variable meta. Finally at S118, the value of the metastable state of the variable meta is outputted to an output Qout of the sequential circuit. Also, if the value of the metastable state flag is not “false”=it is not in the metastable state (S114: No), the metastable state flag is set to “true” at S119. Then, the processes at S116, 5117 and S118 similar to the above-mentioned explanation are performed in turn.
However, the metastable state implies that the output signal becomes unstable (metastable) because a setup time or a hold time does not meets the requirement of the input signal of a latch or flip-flop (FF). When an external asynchronous signal is synchronized in the flip-flop, a time when the input signal is changed is not identified. Thus, it is difficult to avoid the occurrence of the metastable state. However, if a situation of the occurrence of the metastable state can be checked, it is possible to design the configuration of the circuit where there is no problem even though the metastable state may occur. Here, the value of the metastable state is exemplified as a random number, any fixed value, a pseudo random number based on a certain initial value, and the like.
In the processes at S120, S123, the value of the metastable state flag is set to the value showing that it is not in the metastable state=“false”, similarly to the foregoing S115. In the process at S121, the value of the input data Din to the sequential circuit is hold in the variable d, similarly to the foregoing S116. In the process at S122, the value held in the variable d is outputted to the output Qout of the sequential circuit. Consequently, in the process at S116 after the metastable state detecting process at S114, the operation for holding the input data different from each other, between the sequential circuits where the same data signals triggered by the same clock signal are used as the input data. In addition, in the series of the processes at S117 and S118, the operation for outputting the value of the metastable state can be carried out in the event that the value of the input data is changed from the value of the previous time when the clock signal is active.
Also, in the series of the processes at S120, S121 and S122 after the input data change detecting process at S113, the operation can be carried out in the case that the value of the input data is not changed from the value of the previous time when the clock signal is active. In addition, in the series of the processes at S123, S122 after the clock signal active edge detecting process at S112, the operation can be carried out when the clock signal is inactive. Thus, after the value of the metastable state is outputted, it is possible to carry out the operation for outputting the held input data from the inner array element after a next one time.
FIG. 2 is a view showing a conventional configuration of a function block to carry out the operation flow of FIG. 1. A sequential circuit 101 simulates the usual FF operation, correspondingly to the sequential circuits FF1 to FF3. The sequential circuit 101 includes an input data holder 102, a metastable state value generator 103 and a switching controller 104. The input data holder 102 holds the input data Din. The metastable state value generator 103 generates the metastable state value. The switching controller 104 determines an output Dout of the sequential circuit, in accordance with the function simulation operation flow of FIG. 1, at a basic cycle unit, on the basis of the held input data and the generated metastable state value. Here, the basic cycle is equal to or less than one cycle of the clock.
A case of applying the function simulation operation flow of FIG. 1 to a certain asynchronous circuit will be described below.
FIG. 3 is a circuit diagram showing an example of the asynchronous circuit to which the function simulation operation flow is applied. This asynchronous circuit includes FF1, FF2 and FF3 as the sequential circuits, and an adder ALU1. An input data D1 of FF1 is a value after +1 is added to an output data Q1 of FF1 by the adder ALU1. An input data D2 of FF2 and an input data D3 of FF3 are an output data Q1 of FF1. A clock signal CLK1 is sent to FF1. A clock signal CLK2 is sent to FF2 and FF3. That is, the input signal of FF1 is the clock signal CLK1 and the input data D1, and its output signal is the output data Q1. The input signal of FF2 is the clock signal CLK2 and an input data D2 (=Q1), and its output signal is an output data Q2. The input signal of FF3 is the clock signal CLK2 and an input data D3 (=Q1), and its output signal is an output data Q3. Also, a metastable state flag MF1 of FF1, a metastable state flag MF2 of FF2 and a metastable state flag MF3 of FF3 are defined.
FIG. 4 is a timing chart showing states of each signal in the function simulation operation flow. The lateral axis indicates a time. Here, CLK1, D1, Q1, and MF1 are mainly related to FF1. CLK2, D2, Q2, and MF2 are mainly related to FF2. CLK2, D3, Q3, and MF3 are mainly related to FF3. As shown in FIG. 4, the clock signal CLK1 is assumed to be changed for each 3 number of times, and the clock signal CLK2 is assumed to be changed for each 4 number of times.
At first, in the sequential circuit FF1, the value, in which +1 is added to the output Q1 (=0) of Qout of FF1 by the adder ALU1, is supplied as the input data D1 (=1). Then, the values in the 3 number of times, in short, the value (=1) at the time t0, the value (=1) at the time t1 and the value (=1) at the time t2 are held in the inner array element (S111). Next, at the time t3, a rising edge of CLK1 is active (S112: Yes), and the value (=1) of D1 is changed from the value of the previous time (namely, the value (=0) of the initial state of FF1) (S113: Yes). Here, in the initial state, MF1 is “false” (=0) (S114: No). Thus, the value of the metastable state flag MF1 of FF1 at the time t3 becomes “true” (=1) (S119). Then, the value (for example, =1) at any time (for example, =time t2) in the inner array element of FF1 is selected as a usual value d (S116). After that, the value meta (=6) of the metastable state is generated (S117), and the value (=6) of the metastable state is outputted from Qout to Q1 (S118).
In succession, at the time t4, the rising edge of CLK1 becomes inactive (S112, No). Thus, the value of the metastable state flag MF1 of FF1 becomes “false” (−0) (S123). After that, the value at any time selected in the inner array element of FF1, namely, the usual value d (=1) is outputted as the output Q1 (S122).
Similarly, at the times t9, t10, the times t15, t16 and the times t21, 22, in one clock cycle, the value of the metastable state flag MF1 becomes “true” (=1) (S119). Then, at the output Q1 of Qout, the values (respectively, 4, 4 and 5) of the metastable states are outputted (S118). After that, the value at any one time between the 3 number of times held in the inner array element (=d) is outputted as the usual value (S122).
Next, the sequential circuit FF2 receives the input data D2 having the same value as the output Q1 of FF1. Then, similarly to FF1, the values between the 3 number of times of the input data D2, in short, the value (=0) at the time t1, the value (=0) at the time t2 and the value (=6) at the time t3 are held in the inner array element (S111). Next, at the time t4, a rising edge of CLK2 is active (S112: Yes), and the value (=6) of D2 is changed from the value of the previous time (namely, the value (=0) of the initial state of FF2) (S113: Yes). Here, in the initial state, MF2 is “false” (=0) (S114: No). Thus, the value of the metastable state flag MF2 of FF2 at the time t4 is “true” (=1) (S119). Then, the value (for example, =0) at any time (for example, =time t1) in the inner array element of FF2 is selected as the usual value d (S116). After that, the value meta (=3) of the metastable state is generated (S117), and the value (=3) of the metastable state is outputted from Qout to Q2 (S118).
In succession, at the time t5, the rising edge of CLK3 becomes inactive (S112: No). Thus, the value of the metastable state flag MF2 of FF2 becomes “false” (=0) (S123). After that, the value at any time selected in the inner array element of FF2, namely, the usual value d (=0) is outputted as the output Q2 (S122).
At the times t12, t13 and the times t20, t21, when the rising edge of CLK2 is active (S112: Yes), there is no change in the value of D2 (S113: No) Thus, in one clock cycle, the value of the metastable state flag MF2 becomes “false” (=0) (S120), and at the output Q2 of Qout, the value of the finally held time (t11/t19) in the 3 number of times (t9, t10, t11/t17, t18, t19) held (S121) in the inner array element is outputted as the usual value d (S122).
Next, the sequential circuit FF3 receives the input data D3 having the same value as the output Q1 of FF1. Then, similarly to FF1, the values between the 3 number of times of the input data D3, in short, the value (=0) at the time t1, the value (=0) at the time t2 and the value (=6) at the time t3 are held in the inner array element (S111). Next, at the time t4, the rising edge of CLK2 is active (S112: Yes), and the value (=6) of D3 is changed from the value of the previous time (namely, the value (=0) of the initial state of FF3) (S113: Yes). Here, in the initial state, MF3 is “false” (=0) (S114: No). Thus, the value of the metastable state flag MF3 of FF3 at the time t4 is “true” (=1) (S119). Then, the value (for example, =6) at any time (for example, =time t3) in the inner array element of FF3 is selected as the usual value d (S116). After that, the value meta (=7) of the metastable state is generated (S117), and the value (=7) of the metastable state is outputted from Qout to Q3 (S118).
In succession, at the time t5, the rising edge of CLK2 becomes inactive (S112: No). Thus, the value of the metastable state flag MF3 of FF3 becomes “false” (=0) (S123). After that, the value at any time selected in the inner array element of FF3, namely, the usual value d (=6) is outputted as the output Q3 (S122).
At the times t12, t13 and the times t20, t21, when the rising edge of CLK2 is active (S112: Yes), there is no change in the value of D3 (S113: No). Thus, in one clock cycle, the value of the metastable state flag MF3 becomes “false” (=0) (S120), and at the output Q3 of Qout, the value of the finally held time (t11/t19) in the 3 number of times (t9, t10, t11/t17, t18, t19) held (S121) in the inner array element is outputted as the usual value d (S122).
Here, the sequential circuits FF2, FF3 at the time t4 capture the values of the output Q1 of FF1, which are the same data signal, through the rising edge of CLK2 as the input data D2, D3. However, the values selected at any time from the inner array element held as the values in the 3 number of times, respectively, are the different values, such as the value (=0) of the time t1 at FF2 and the value (=6) of the time t3 at FF3. Thus, this indicates the occurrence of the phenomenon that the values held between the sequential circuits FF2, FF3 are different.
This fact indicates that at the timing of the time t4, when a time difference between a signal transmission delay of the input data D2 to FF2 and a signal transmission delay of the input data D3 to FF3 is simulated, the same data signal triggered by the same clock signal involves a trouble operation caused by a timing problem between the input sequential circuits.
Also, the value (=6) of the D3 selected as the usual value by FF3 is the value of the metastable state generated in the sequential circuit FF1. Thus, this implies that the originally expected input data, namely, the value different from the value (=1) of the output Q1 at the time t4 is inputted to FF3. Thus, from the time t5 to the time t12, this asynchronous circuit results in the trouble operation. The change of CLK1 at the time t3 and the change of CLK2 at the time t4 indicate the timings when the trouble operation occurs in this asynchronous circuit.
As mentioned above, the method of verifying the asynchronous circuit in Japanese Laid Open Patent Application (JP-P 2003-233638A) discloses the operation of the circuit configuration where the output data of the plurality of sequential circuits, in which the cycles of the clock signals are different, mutually serve as the input data of the sequential circuits.
The foregoing conventional method of verifying the asynchronous circuit determines the output values of the sequential circuits, in accordance with the function simulation operation flow (conventional algorithm), on the basis of the input data to the sequential circuit FF and the value of the metastable state, in one basic cycle unit of the function simulation. That is, a reset signal that can be supplied to the sequential circuit FF is not considered. For this reason, this verifying method does not change the output value for the sequential circuit including the asynchronous reset signal. Thus, it is difficult to properly execute the function simulation of the sequential circuit while considering the asynchronous reset signal. A technique that can properly execute the function simulation of the sequential circuit regardless of the reset signal and the clock signal is desired.
The conventional method of verifying the asynchronous circuit requires the inner array elements D[0] to D[n] to hold the input data before the n number of times, and they are required for each sequential circuit having the different cycle of the clock signal. For this reason, as the circuit size of the verification target becomes bigger, the memory amount consumed for the inner array elements when the circuit simulation is executed becomes greater. Usually, there is the limit in the memory resource of the computer for executing the function simulation. For this reason, its amount limit leads to the restriction on the circuit size to which the conventional technique can be applied. A technique that can execute the circuit simulation in which the memory use amount is suppressed is desired.